Design, Modeling and Analysis of Cu-Carbon Hybrid Interconnects

Design, Modeling and Analysis of Cu-Carbon Hybrid Interconnects

Blog Article

In this work, a new interconnect structure is proposed for the first time where copper-carbon nanotube composite interconnect is encapsulated by graphene barrier layers named here as copper-carbon (Cu-carbon) hybrid interconnects.The motivation behind this new structure is to utilize the enhanced conductivity of copper-carbon nanotube (Cu-CNT) composite Dishwasher Lower Tray and improved reliability of copper-graphene (Cu-GNR) hybrid in order to build a better interconnect structure for possible replacement of copper interconnects in near future VLSI applications.The steps required to fabricate this structure is also proposed by utilizing the fabrication methods of Cu-CNT composite and Cu-GNR hybrid materials.First-principles-based atomistic simulations suggest that Cu-Carbon hybrid structure is more conductive than its parent structures, i.e.

Cu-CNT composite and Cu-GNR hybrid.This deduction is also supported by the circuit simulation results at 7 nm node which show that Cu-Carbon hybrid interconnect experiences least delay among all other Girls Jewelry alternatives.When compared to Cu-GNR, Cu-CNT and Cu interconnects, delay in 1 mm long Cu-Carbon hybrid interconnect is lesser by ~28%, ~41% and ~88%, respectively.Time-domain analysis suggests that Cu-Carbon hybrid interconnect has the steepest and sharpest step response.Cu-Carbon hybrid interconnect has proven to be superior than other alternatives in terms of signal integrity.

Noise-delay-product in a 1 mm long Cu-Carbon hybrid is lesser by ~42%, ~47% and ~84% as compared to Cu-GNR, Cu-CNT and Cu interconnects, respectively.Power consumption is also least in Cu-Carbon hybrid interconnects.Power-delay-product in a 1 mm long Cu-Carbon hybrid is also reduced by ~41%, ~44% and ~43% as compared to Cu-GNR, Cu-CNT and Cu interconnects, respectively.These findings promote Cu-Carbon hybrid interconnect as a superior candidate for near future VLSI applications.